USB v2.0 Soft PHY and Device Controller
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
PhyWhisperer-USB | Crowd Supply
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Partitioning hi-speed USB systems - EE Times
HSIC USB 2.0 PHY IP
PCIe/USB/SATA PHY Application Example | Renesas
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB2 Controller | Cadence
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Usb3300 Usb Hs Board Host Otg Phy Low Pin Ulpi Evaluation Development Module Kit - Integrated Circuits - AliExpress
Difference between USB and ULPI - Electrical Engineering Stack Exchange
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
The Next-Generation Interconnect | Mouser
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USB 2.0 PHY Verification
PhyWhisperer-USB - NewAE Hardware Product Documentation
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
PhyWhisperer-USB | Crowd Supply
USB2 PHY | Cadence
USBPHYC internal peripheral - stm32mpu
